ChipInsight

ChipInsight™ enables better, faster 2D validation of integrated circuit designs based on real, actual wafer contours, not a model. Since, as they say “All models are wrong, but some are useful” using actual wafer prints for 2D validation guarantees that any hotspots detected with ChipInsight are real.

Validation and correction require multiple steps using today’s tools. With ChipInsight, validation and correction can be started sooner, and completed sooner, for critical modules, large areas and/or full chip layers. With ChipInsight, after taking a CDSEM map of the critical area, ChipInsight extracts the actual wafer contours and identifies mismatches with the design intent, so modules can be checked and mask patterns corrected.

ChipInsight’s powerful image-based system can process and analyze multiple, overlaid layers of aligned and stitched SEM image arrays using a High-Performance Image Analysis Server Platform. ChipInsight uses parallel computing with a multi-core architecture and can process image arrays of essentially unlimited size.

The technologies implemented in ChipInsightâ„¢ represent a step forward from single-image validation and model-only checks. ChipInsight enables image-based analysis of large areas at full resolution with immediate access to all the features on all of the images by multiple users via web interface. Overlaying the target design data and comparing it to the XFOV contours extracted from the array of CD-SEM images allows identification of hotspots automatically. Viewing the features and the design overlayed on any/all features can be done by multiple users, simultaneously. Every feature is available for review and analysis. ChipInsightâ„¢ can automatically read image streams from all major CD-SEM manufactures.

ChipInsight reconstructs arrays of top-down SEM images, and assemble them into a single 3D model, automatically extracting features, and exporting contours to GDSII or other EDA formats. An array of 2D problems can be solved, for example, you can determine pullback or extension of the actual printed pattern versus the design intent. With 2D studies like line-ends, you can compare the actual extension or pullback versus the design and comparing like-features across the chip can aid in building new OPC models. Large features, that span multiple CD-SEM images, can also be easily studied. Users can review, comment and edit results via secure web-based interface with interactive collaboration features.

Applications include:

• 2D pattern validation
• 2D OPC model building
• 3D circuit model building
• Failure Analysis
• Reverse Engineering and IP protection